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1 ?2016 integrated device technology, inc revision b february 8, 2016 910111213141516 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 gnd divsel_a in v t v ref_ac nin divsel_b divsel_c en v dd nqb2 qb2 nqb1 nqb0 qb0 qb1 qa3 nqa3 v dd gnd gnd v dd qc nqc nmr v dd qa0 nqa0 qa1 qa2 nqa2 nqa1 general description the 8S89200 is a high speed 1-to-8 differential-to-lvds clock divider and is part of the high performance clock solutions from idt. the 8S89200 is optimized for high speed and very low output skew, making it suitable for use in demanding applications such as sonet, 1 gigabit and 10 gigabit ethernet, and fibre channel. the internally terminated differential inputs and v ref_ac pins allow other differential signal families such as lvpecl, lvds and cml to be easily interfaced to the input with minimal use of external components. the device also has a selectable 1, 2, 4 output divider, which can allow the part to support multiple output frequencies from the same reference clock. the 8S89200 is packaged in a small 5mm x 5mm 32-pin vfqfn package which makes it ideal for use in space-constrained applications. features ? three output banks, consisting of eight lvds output pairs total ? inx, ninx inputs can accept the following differential input levels: lvpecl, lvds, cml ? selectable output divider values of 1, 2 and 4 ? maximum output frequency: 1.5ghz ? maximum input frequency: 3ghz ? bank skew: 10ps (typical) ? part-to-part skew: 100ps (typical) ? additive phase jitter, rms: 0.170ps (typical) ? propagation delay: 802ps (typical) ? output rise time: 150ps (typical) ? 2.5v5% operating supply voltage ? -40c to 85c ambient operating temperature ? available in lead-free (rohs 6) package 32-lead 5mm x 5mm vfqfn pin assignment 8S89200 8S89200 data sheet low skew, 2:1 lvds mux with 1:8 fanout and internal termination
block diagram in nin v ref_ac qa0 nqa0 v t qa1 nqa1 qa2 nqa2 qa3 nqa3 qc nqc 1 2 4 1 2 2 2 4 4 qb0 nqb0 qb1 nqb1 qb2 nqb2 divsel_a divsel_b divsel_c en nmr pullup pullup pullup pullup pullup r in =50 ? r in =50 ?
3 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet table 1. pin descriptions note: pullup refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 20, 21 gnd power ground supply pins. 2 divsel_a input pullup output divider select pin. controls output divider settings for bank a. see table 3 for additional information. lvcmos/lvttl interface levels. 3 in input non-inverting differen tial lvpecl clock input. r in = 50 ? termination to v t. 4 v t input termination center-tap input. 5 v ref_ac output reference voltage for ac-coupled applications. 6 nin input inverting differential lvpecl clock input. r in = 50 ? termination to v t. 7 divsel_b input pullup output divider select pin. controls output divider settings for bank b. see table 3 for additional information. lvcmos/lvttl interface levels. 8 divsel_c input pullup output divider select pin. controls output divider settings for bank c. see table 3 for additional information. lvcmos/lvttl interface levels. 9 en input pullup output enable pin. see table 3 for additional information. lvcmos/lvttl interface levels. 10, 19, 22, 31 v dd power positive supply pins. 11, 12 nqb2, qb2 output differential out put pair. lvds interface levels. 13, 14 nqb1, qb1 output differential output pai r. lvds interface levels. 15, 16 nqb0, qb0 output differential out put pair. lvds interface levels. 17, 18 nqc, qc output differential output pai r. lvds interface levels. 23, 24 nqa3, qa3 output differential out put pair. lvds interface levels. 25, 26 nqa2, qa2 output differential output pai r. lvds interface levels. 27, 28 nqa1, qa1 output differential out put pair. lvds interface levels. 29, 30 nqa0, qa0 output differential output pai r. lvds interface levels. 32 nmr input pullup master reset. see table 3 for additional information. lvcmos/lvttl interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 2pf r pullup input pullup resistor 25 k ?
4 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet function tables table 3. sel function table figure 1a. reset with output enabled nmr en divsel_a divsel_b divsel_c output ba nk a output bank b output bank c 0 n/a n/a n/a n/a 0 0 0 1 0 n/a n/a n/a 0 0 0 11 0 0 0 1 2 2 11 1 1 1 2 4 4 q,1 q05 (1 q4 4 q4 4 2xwsxw 2xwsxw 2xwsxw ,1 q,1 ,1 q05dv\qfkurqrxvo\uhvhwvwkhrxwsxwv 9 '' 2xwsxwvjr+,*+vlpxowdqhrxvo\diwhufrpsohwhlqsxwforfn,1 shulrgvdiwhuq05lvghdvvhuwhg w 3' 054 w 55 q4 4
5 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet figure 1b. enabled timing nin en nq q nq q 1 output 2 output 4 output in nin in 1234 enabled asserted v dd /2 outputs go high simultaneously after en is asserted. the number of in clock cycles after en is asserted before the outputs go high varies from 2 to 6 cycles (4 cycles shown). nq q
6 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet figure 1c. disabled timing nin en nq q nq q 1 output 2 output 4 output in nin in 1234 enabled de-asserted to disable q[0:7] outputs v dd /2 outputs go low in output sequence after en is de-asserted. the 4, 2and 1 outputs go low in that order. the number of in clock cycles after en is de-asserted varies from 2 to 6 cycles (4 cycles shown). q nq
7 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only . functional operation of product at t hese conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c table 4b. lvcmos/lvttl dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c table 4c. differential dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, i o continuous current surge current 10ma 15ma input current, in, nin 50ma v t current, i vt 100ma input sink/source, i ref_ac 2ma package thermal impedance, ? ja 42.7 ? c/w (0 mps) storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 2.375 2.5 2.625 v i dd power supply current 280 311 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage 1.7 v dd + 0.3 v v il input low voltage -0.3 0.7 v i ih input high current v dd = v in = 2.625v -125 20 a i il input low current v dd = 2.625v, v in = 0v -300 ua symbol parameter test conditio ns minimum typical maximum units r in input resistance in, nin in to vt, nin to vt 50 ? v ih input high voltage in, nin 0.15 v dd + 0.3 v v il input low voltage in, nin 0 v dd ? 0.15 v v in input voltage swing 0.15 1.2 v v diff_in differential input vo ltage swing 0.3 2.4 v v ref_ac bias voltage v dd ? 1.34 v dd ? 1.3 v dd ? 1.18 v
8 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet table 4d. lvds dc characteristics, v dd = 2.5v 5%, t a = -40c to 85c ac electrical characteristics table 5. ac characteristics, v dd = 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature rang e, which is established when th e device is mounted in a test socket with maintained transverse airflow greate r than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from the differential input crossi ng point to the differential output crossing point. note 2: this parameter is defined in accordance with jedec standard 65. note 3: defined as skew between outputs at the same supply volt age and with equal load conditions. measured at the output diffe rential cross points. note 4: defined as skew within a bank of outputs at the same voltage and with equal load conditions. note 5: defined as skew between outputs on different devices o perating at the same supply voltage , same temperature, same frequ ency and with equal load conditions. using the same type of inputs on each device, the outputs are measured at the differential cross po ints. symbol parameter test conditio ns minimum typical maximum units v od differential output voltage 312 375 483 mv ? v od vod magnitude change 50 mv v os offset voltage 1.14 1.25 1.40 v ? v os vos magnitude change 50 mv symbol parameter test conditio ns minimum typical maximum units f out output frequency 1.5 ghz f in input frequency 3ghz t pd propagation delay; note 1 in to qx 650 802 935 ps nmr to qx 500 725 965 ps tsk(b) bank to bank skew; note 2, 3 same divide setting 10 55 ps tsk(w) bank to bank skew; note 2, 3 different divide setting 80 150 ps tsk(o) within-bank skew; note 2, 4 within same fanout bank 4 25 ps tsk(pp) part-to-part skew; note 2, 5 250 ps t jit buffer additive phase jitter, rms; refer to additive p hase jitter section 156.25mhz, integration range: 12khz to 20mhz 0.170 0.214 ps t r / t f output rise/fall time 20% to 80% 80 150 210 ps
9 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. measured using a rohde & schwarz sma100 as the input source. offset from carrier frequency (hz) ssb phase noise dbc/hz
10 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet parameter measureme nt information output load ac test circuit propagation delay offset voltage setup input levels output rise/fall time differential output voltage setup v dd t pd nqax, nqbx, nqc qax, qbx, qc nin in v ih cross points v in v il in nin v cc v ee nqax, nqbx, nqc qax, qbx, qc 20% 80% 80% 20% t r t f v od
11 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet parameter measurement in formation, continued within bank skew bank to bank skew (same divide setting) part-to-part skew bank to bank (different divide settings) single-ended & differential input swing qx nqx qy nqy t sk(b) qxx nqxx qxy nqxy where x = bank a, bank b or bank c v in v diff_in differential voltage swing = 2 x single-ended v in t sk(pp) part 1 part 2 qx nqx qy nqy tsk( ) qxx nqxx qxy nqxy
12 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet applications information 2.5v lvpecl input with built-in 50 ? termination interface the in/nin with built-in 50 ? terminations accept lvds, lvpecl, cml and other differential signals. both signals must meet the v in and v ih input requirements. figures 2a to 2d show interface examples for the in/nin with built-in 50 ? termination input driven by the most common driver types. th e input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of the driver component to confirm the driver termination requirements. figure 2a. in/nin input with built-in 50 ? driven by an lvds driver figure 2c. in/nin input with built-in 50 ? driven by a cml driver figure 2b. in/nin input with built-in 50 ? driven by an lvpecl driver figure 2d. in/nin input with built-in 50 ? driven by a cml driver with built-in 50 ? pullup
13 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? and 132 ? . the actual value should be selected to match the differential impedance (z 0 ) of your transmission line. a typical point-to-point lvds design uses a 100 ? parallel resistor at the receiver and a 100 ? differential transmission-line environment. in order to avoid any transmission-line reflection issues, the components should be surface mounted and must be placed as close to the receiver as possible. idt offers a full line of lvds compliant devices with two types of output structures: current source and voltage source. the standard termination schematic as shown in figure 3a can be used with either type of output structure. figure 3b , which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termination, it is recommended to contact idt and confirm if the output structure is current source or voltage source type. in addition, since these outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the output. recommendations for unused input and output pins inputs: lvcmos select pins all control pins have internal pullups; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvds outputs all unused lvds output pairs can be either left floating or terminated with 100 ? across. if they are left floating, we recommend that there is no trace attached. lvds driver lvds driver lvds receiver lvds receiver z t c z o ? z t z o ? z t z t 2 z t 2 figure 3a. standard termination figure 3b. optional termination
14 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 4. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board through a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern must be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal land. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally /electrically enhance leadframe base package, amkor technology. figure 4. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
15 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet power considerations this section provides information on power dissi pation and junction temperature for the 8S89200. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8S89200 is the sum of the core power plus the power dissipated in the load(s). the followin g is the power dissipation for v dd = 2.5v + 5% = 2.625v, which gives worst case results. the maximum current at 85c is as follows: i dd_max = 281ma ? power (core) max = v dd_max * i dd_max = 2.625v * 311ma = 816.375mw ? power dissipation for internal termination r t power (r t ) max = (v in_max ) 2 / r t_min = (1.2v) 2 / 80 ? = 18mw total power_ max = (2.625v, with all outputs switching) = 816.375mw + 18mw = 816.393mw 2. junction temperature. junction temperature, tj, is the temperatur e at the junction of the bond wire and bo nd pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ? ja * pd_total + t a tj = junction temperature ? ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ? ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 42.7c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.816w * 42.7c/w = 120c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ? ja for 32 lead vfqfn, forced convection ? ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 42.7c/w 37.3c/w 33.5c/w
16 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet reliability information table 7. ? ja vs. air flow table for a 32 lead vfqfn transistor count the transistor count for 8S89200: 689 ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 42.7c/w 37.3c/w 33.5c/w
17 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet 32 lead vfqfn package out line and package dimensions package outline - k suffix for 32 lead vfqfn table 8. package dimensions note: the following package mechanical drawing is a generic drawing that applies to any pin count vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pin-out are shown on the front page. the package dimensions are in table 8. reference document: jede c publication 95, mo-220 to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or anvil s ing u l a tion n-1 n chamfer 1 2 n-1 1 2 n radius 4 4 bottom view w/type c id bottom view w/type a id there a re 2 method s of indic a ting pin 1 corner a t the ba ck of the vfqfn p a ck a ge: 1. type a: ch a mfer on the p a ddle (ne a r pin 1) 2. type c: mo us e b ite on the p a ddle (ne a r pin 1) jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum nominal maximum n 32 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.25 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.40 0.50
18 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet ordering information table 9. ordering information table 10. pin 1 orientation in tape and reel packaging part/order number marking package shipping packaging temperature 8S89200bkilf ics89200bil 32 lead vfqfn, lead-free tray -40 ? c to 85 ? c 8S89200bkilft ics89200bil 32 lead vfqfn, lead-free tape & reel -40 ? c to 85 ? c 8S89200bkilf/w ics89200bil 3 2 lead vfqfn, lead-free tape & reel pin 1 orientation: eia-481-d -40 ? c to 85 ? c part number suffix pin 1 orientation illustration lft quadrant 1 (eia-481-c) lf/w quadrant 2 (eia-481-d) u s er direction of feed correct pin 1 orientation carrier tape top s ide (ro u nd s procket hole s ) u s er direction of feed correct pin 1 orientation carrier tape top s ide (ro u nd s procket hole s )
19 ?2016 integrated device technology, inc revision b february 8, 2016 8S89200 data sheet revision history sheet rev table page description of change date b t9 t10 18 18 ordering information table - added additional row. added pin 1 orientation in tape & reel packaging table. updated header/footer throughout the data sheet. 06/08/2015 b t9 18 ordering information - removed lf note below table. updated header and footer. 2/8/16
disclaimer integrated device technology, in c. (idt) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of idt's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not conv ey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . copyright ?2016 integrated device tec hnology, inc. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com 8S89200 data sheet

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